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hi-8685, hi-8686 arinc interface device arinc 429 & 561 serial data to 16-bit parallel data description the hi-8685 and hi-8686 are system components for interfacing incoming arinc 429 signals to 16-bit parallel data using proven +5v analog/digital cmos technology. both products incorporate the digital logic and analog line receiver circuitry in a single device. the receivers on the hi-8685 and the hi-8686 connect directly to the arinc 429 bus and translate the incoming signals to normal cmos levels. internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. the -10 version of the hi-8685 allows the incorporation of an external 10k resistance in series with each arinc input for lightning protection without affecting arinc level detection. both products offer high speed 16-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. a reset pin is also provided for power-on initialization. automatic conversion of serial arinc 429, 575 & 561 data to 16-bit parallel data high speed parallel 16-bit data bus error detection - and on-chip line receiver input hysteresis of at least 2 volts test lnputs bypass analog inputs simplified lightning protection with the ability to add 10 kohm external series resistors small, package options: soic, pqfp and plcc industrial and extended temperature ranges word length parity reset input for power-on initialization surface mount, plastic features pin configurations (top view) december 2008 hi-8685 28-pin plastic soic - wb package hi-8686 32-pin plastic pqfp package hi-8686pqi hi-8686pqt 24 - 23 - rinb-10 22 - rinb 21 - rina 20 - rina-10 19 - error 18 - parity enb 17 - n/c reset hi-8685psi hi-8685pst & hi-8685psi-10 hi-8685pst-10 datardy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 gnd vcc gapclk testa testb rinb (-10) rina (-10) error parity enb d0 d1 d2 d3 reset read 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n/c - 1 d12-2 d11-3 d10-4 d9-5 d8-6 d7-7 d6-8 d5 - 9 d4 - 10 gnd - 11 d3 - 12 d2 - 13 d1 - 14 d0 - 15 -16 read 32 - d13 31 - d14 30 - d15 29 - datardy 28 - 27 - gapclk 26 - testa 25 - testb vcc (ds8685 rev. n) 12/08 applications avionics data communication serial to parallel conversion parallel to serial conversion (see page 8 for additional pin configurations) holt integrated circuits www.holtic.com
hi-8685, hi-8686 pin descriptions data rdy output receiver data ready flag. a high level indicates data is available in the receive buffer. flag goes low when the first 16-bit byte is read. d0 to d15 output 16-bit parallel data bus (tri-state) gnd power 0v input read strobe. a low level transfers receive buffer data to the data bus parity enb input parity enable - a high level activates odd parity checking which replaces the 32nd arinc bit with an error bit. otherwise, the 32nd arinc bit is unchanged error output error flag. a high level indicates a bit count error (number of arinc bits was less than or greater than 32) and/or a parity error if parity detection was enabled (parity enb high) rina/rina-10 input positive direct arinc serial data input rinb/rinb-10 input negative direct arinc serial data input (both rinb and rinb-10 on hi-8686) input internal logic states are initialized with a low level testa input used in conjunction with the testb input to bypass the built-in analog line receiver circuitry testb input u gapclk input gap clock. determines the minimum time required between arinc words for detection. the minimum word gap time is between 16 and 17 clock cycles of this signal. vcc power +5v 5% supply signal function description read reset (both rina and rina-10 on hi-8686) sed in conjunction with the testa input to bypass the built-in analog line receiver circuitry functional description the hi-8685 and hi-8686 are serial to 16-bit parallel con- verters. the incoming data stream is serially shifted into an input register, checked for errors, and then transferred in par- allel to a 32-bit receive buffer. the receive data can be ac- cessed using two 16-bit parallel read operations while the next serial data steam is being received. the block diagram for both the hi-8685 and hi-8685-10 products is found in figure 1. both have built-in receivers eliminating the need for additional external arinc level de- tection circuitry. the only difference between the two prod- ucts is the amount of internal resistance in series with each arinc input. internal 35k resistors are in series with both the rina and rinb arinc 429 inputs. they connect to level translators whose resistance to gnd is typically 10k after level receiver inputs hi-8685 arinc inputs (rina & rinb) . translation, the buffered inputs drive a differential amplifier. the differential signal is compared to levels derived from a divider between vcc and gnd. the nominal settings cor- respond to a one/zero amplitude of 6.0v and a null ampli- tude of 3.3v. a valid arinc one/zero input sets a latch and a null input resets the latch. since any added external series resistance will affect the voltage translation, the hi-8685-10 product has only 25k of the 35k series resistance required for proper arinc 429 level detection. the remaining 10k required is avail- able to the user for incorporation in external circuitry such as for lightning protection. the hi-8686 has both sets of arinc inputs, rina/rina-10 and rinb/rinb-10 available to the user. hi-8685-10 arinc inputs (rina-10 & rinb-10) hi-8686 arinc inputs holt integrated circuits 2
hi-8685, hi-8686 protocol detection the arinc clock and one/zero data that are derived from the outputs of the built-in line receiver is illustrated in figure 3. the resulting steam of digital data is shifted into a 32-bit input register. the arinc clock and one/zero data can also be created from the testa and testb inputs as shown in figure 4. when either test input is high, the built-in analog line driver is disabled. digital for arinc 561 operation, the testa and testb digital in- put data streams must be derived from the arinc 561 data, clock and sync with external logic. gap detection the end of a data word is detected by an internal counter that times out when a data one or zero is not received for a period equal to 16 cycles of the gapclk signal. the gap detection time may vary between 16 and 17 cycles of the gapclk signal since the incoming data and gapclk are not usually synchronous inputs. the required frequency of gapclk is a function of the mininum gap time specified for the type of arinc data being received. table 1 indicates typical frequencies that may be used for the various data rates normally encountered. bit count parity detect gap detect 32-bit shift reg. 32-bit receive buffer 32-bit to 16-bit mux error detect clock & data detect parity enb rinb testa testb gapclk reset byte count read data rdy error 32 16 32 figure 1. block diagram esd protection & line receiver databus bit period minimum gap gap clock gap detection type (s) (s) mhz time (s) 429 10 45 0.75 21.3 - 22.7 1.0 16 - 17 1.5 10.7 - 11.3 429 69 - 133 310 - 599 0.1 160 - 170 575 69 - 133 310 - 599 0.1 160 - 170 561 69 - 133 103 - 200 0.2 80 - 85 table1-t ypical gap detection times functional description (cont.) rxa rxb 10k bit 32 bit 32 rina 10k d0 - d15 25k 25k rinb-10 rina-10 data clk holt integrated circuits 3
hi-8685, hi-8686 error checking reading receive buffer once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. when parity detection is enabled (parity enb high), the received word is checked for odd parity. if there is a parity error, the 32nd bit of the received data word is set high. if parity checking is disabled (parity enb low) the 32nd bit of the data word is always the 32nd arinc bit re- ceived. the error flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. the error flag is reset low when the next valid arinc word is written into the receive buffer or when is pulsed low. when the data word is transferred to the receive buffer, the data rdy pin goes high. the data word can then be read in two 16-bit bytes by pulsing the input low as indicated in figure 5. the first read cycle resets datardy low and increments an internal counter to the second 16-bit byte. the relationship between each bit of an arinc word received and each bit of the two 16-bit data bus bytes is specified in figure 2. when a new arinc word is received it always overwrites the receive buffer. if the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new arinc word. how- ever, if the datardy pin goes high between the reading of the first and second bytes, the first byte is no longer valid because the corresponding second byte has been overwritten by the new arinc word. also, the next read will be of the first byte of the new arinc word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. reset read functional description (cont.) truth table 1. rina (-10) rinb (-10) testa testb rxa rxb -1.50v to +1.50v -1.50v to +1.50v 0 0 0 0 -3.25v to -6.50v +3.25v to +6.50v 0 0 0 1 +3.25v to +6.50v -3.25v to -6.50v 0 0 1 0 x x 0101 x x 1010 x x 1100 x = don't care read byte data bus bits arinc bits 1st byte 1 d0 - d15 arinc 1 - arinc 16 2nd byte 2 d0 - d15 arinc 17 - arinc 32 figure 2. order of received data reset test mode a low on the input sets a flip-flop which initializes the internal logic. when goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. the built-in differential line receiver can be disabled allow- ing the data and clock detection circuitry to be driven di- rectly with digital signals. the logical or function of the testa and testb is defined in truth table 1. the two in- puts can be used for testing the receiver logic and for input- ting arinc 429 type data derived from another source / pro- tocol. see figure 4 for typical test input timing. the device should always be initialized with imme- diately after entering the test mode to clear a partial word that may have been received since the last word gap. oth- erwise, an error condition may occur and the first 32 bits of data on the test inputs may not be properly received. also, when entering the test mode, both testa and testb should be set high and held in that state for at least one word gap period (17 gap clocks) after goes high. when exiting the test mode, both test inputs should be held low and the device initialized with reset reset reset reset reset. holt integrated circuits 4
hi-8685, hi-8686 figur e 5 - receiver parallel databus timing data rdy read d0 - d15 valid t rdyclr t rdpw t rr t fd t rd valid 1st 16-bits 2nd 16-bits t drdy derived data arinc data bits word gap 28 29 30 31 32 1 2 4 bit periods min. testa +5v 0v testb 0v +5v derived clock derived data arinc data bits word gap 28 29 30 31 32 1 2 4 bit periods min. vdiff rina - rinb 0v +10v -10v figur e 3 - receiver input timing for arinc 429 derived data derived clock timing diagrams figur e 4 - test input timing for arinc 429 32nd arinc bit holt integrated circuits 5
parameters symbol test conditions min typ max units arinc bus inputs digital inputs (rina, rinb, rina-10 & rinb-10) differential input voltage one or zero v differential voltage 6.5 10.0 13.0 volts null v " " " " - - 2.75 volts common mode v with respect to gnd - - 5.0 volts input resistance rina (-10) to rinb(-10) r supplies floating 30 75 - kohm rina (-10) or rinb(-10) to gnd or v r " " " ' 19 40 - kohm input capacitance (guaranteed but not tested) differential c rina (-10) to rinb (-10) - - 20 pf to gnd c - - 20 pf to v c - - 20 pf ( , gapclk, & parity enb) input voltage high v 2.0 - v volts low v 0.0 - 0.8 volts input current source i v = 5.0v - - 1.0 a sink i v = 0.0v -1.0 - - a input capacitance c - - 8.0 pf din nin com diff cc sup diff g cc h ih cc il ih in il in i reset read supply voltages v ...................................................+5v temperature range industrial ................................ -40c to +85c hi-temp ............................... -55c to +125c junction temperature, tj ................... +175c cc 5% all voltages referenced to gnd supply voltages v ....................................................... +7.0v voltage on inputs rina (-10) to rinb (-10) ......... +29v to - 29v all other input pins..................-0.3 to vcc +0.3 dc current per input pin ....................... +10ma power dissipation at 25c plastic 28-pin so..... 1.8w, derate 14.1mw/c plastic 28-pin plcc .2.3 plastic 32-pin so......1.6 solder temperature leads ............................. +280c for 10 sec package body ..................................+220c storage temperature ............. -65c to +150c cc w, derate 18.2mw/c w, derate 15.4mw/c note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dc electrical characteristics hi-8685, hi-8686 holt integrated circuits 6
hi-8685, hi-8686 dc electrical characteristics (cont.) parameters symbol test conditions min typ max units digital inputs outputs operating supply current (testa & testb) input voltage high v 2.4 - v low v 0.0 - 0.8 volts input current source -110- sink -1.0 - - input capacitance c - - 8.0 pf (d0 to d15, error & data rdy) output voltage high low i = 1.6 ma - - 0.4 volts output tri-state current (d0 - d15 only) v = 5.0v - - 1.0 a v = 0.0v -1.0 - - output capacitance - - 15 pf v i v = 0.0v, outputs open - - 6.5 ma ih cc il i ol oh ol cc cc in volts i v = 5.0v a i v = 0.0v a v i = -1.0 ma 2.7 - - volts v i ia c ih in il in oh oh ol ih il o parameters symbol test conditions min typ max units pulse width t 50 ns data delay from t 40 ns to data floating t 20 ns to data rdy clear t 35 ns pulse to next pulse t 25 ns gapclk frequency f 1 mhz 32nd arinc bit to data rdy t 16 17 clocks read read read read read read rdpw rd fd rdyclr rr gc drdy ac electrical characteristics vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). vcc = 5v, gnd = 0v, ta = operating temperature range (unless otherwise specified). holt integrated circuits 7
4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 testb rinb (rinb-10) rina (rina-10) error parity enb reset read d13 d14 d15 data rdy v gapclk testa cc hi-8685pji hi-8685pjt & hi-8685pji-10 hi-8685pjt-10 12 13 14 15 16 17 18 d5 d4 gnd d3 d2 d1 d0 d12 d11 d10 d9 d8 d7 d6 hi-8685, hi-8686 ordering information additional hi-8685 pin configuration (see page 1 for additional pin configurations) for hi-8686pq please see next page hi - 8685xx x - xx x package description built-in line recv?r 28 pin plastic wide soic (28hw) yes 28 pin plastic plcc (28j) yes part number 8685ps 8685pj temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank input series resistance built-in required externally part number 25 kohm 10 kohm -10 35 kohm 0 no dash number hi-8685 28-pin plastic plcc holt integrated circuits 8
temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank package description built-in line recv?r ext. 10k required 32 pin plastic pqfp (32pqs) yes optional (1) part number 8686pq hi-8685, hi-8686 ordering information (1) rina / rinb and rina-10 / rinb-10 are both available for hi-8685 please see previous page hi - 8686pq x x holt integrated circuits 9
revision history hi-8685, hi-8686 revision date description of change ds8685, rev. n 12/15/08 replaced 18-pin soic package dimension drawing with correct 28-pin drawing, corrected dimensions for pqfp package to reflect current package vendor, and clarified temperature ranges. holt integrated circuits 10
28-pin plastic plcc inches (millimeters) package type: 28j .045 x 45 .453 .003 (11.506 .076) sq. .490 .005 (12.446 .127) sq. .045 x 45 .173 .008 (4.394 .203) pin no. 1 ident pin no. 1 .410 .020 (10.414 .508) .031 .005 (.787 .127) .017 .004 (.432 .102) .050 (1.27) bsc detail a .035 .889 r .010 .001 (.254 .03) .020 (.508) min see detail a bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 28-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 28hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .706 .004 (17.92 .11) .407 .013 (10.325 .32) .294 .002 (7.486 .05) .050 (1.27) 0 to 8 .033 .017 (.838 .432) .095 .005 (2.413 .127) .0075 .0035 (.191 .089) bsc .018 (.457) typ see detail a detail a .0105 .0015 (.2667 .0381) hi-8685, hi-8686 package dimensions holt integrated circuits 11
32 pin plastic quad flat pack (pqfp) inches (millimeters) package type: 32pqs .354 (9.00) bsc sq .047 (1.20) .004 (.10) .004 .002 (0.10 .05) 0 7 .276 (7.00) bsc sq see detail a detail a max r ref bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .0315 (0.80) .015 .003 (0.375 .075) .039 .002 (1.0 .05) .006 (0.15) .024 .006 (0.60 .15) bsc .006 .002 (0.152 .06) hi-8685, hi-8686 package dimensions r ref holt integrated circuits 12

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